Quartus II 11.1sp2 Web Edition and Model Sim-Altera Starter software are used for this tutorial, which are freely available and can be downloaded from the Altera website. First line of each listing in the tutorial, is the name of the Verilog file in the downloaded zip-folder.Digitals design can be create using two methods i.e. Follow the below steps for pin assignments, Verilog code can be converted into block schematic format, which is quite useful for connecting various modules together.The text files are tab delimited, and are most easily viewed using a spreadsheet program, such as Microsoft Excel.
using ‘block-schematics’ and with ‘programming language e.g. Both have their own advantages in the design-process, as we will observe in the later chapters of the tutorial. Once design is analyzed, then next step is to assign the correct pin location to input and output ports. In this section, half adder’s Verilog file is converted into schematic and then two half adder is connected to make a full adder.
In this section, we will create a half_adder using block-schematics method, as shown below, Note that, ‘start compilation’ option (above the Analyse option in the figure) is used when we want to generate the .sof/file, to load the design on the FPGA, whereas analyze option is used to generate the RTL view only. Note that, this connection can be made using Verilog code as well, which is discussed in In this chapter, we learn to implement the design using schematic and coding methods.
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